ds070 (v2.1) june 1, 2000 www.xilinx.com 1 product specification 1-800-255-7778 ? 2000 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? certified to mil-prf-38535 appendix a qml (qualified manufacturer listing.) also available under the following standard microcircuit drawings (smd): 5962-94717 and 5962-95617. configuration one-time programmable (otp) read-only memory designed to store configuration bitstreams of xilinx fpga devices on-chip address counter, incremented by each rising edge on the clock input simple interface to the fpga requires only one user i/o pin cascadable for storing longer or multiple bitstreams programmable reset polarity (active high or active low) for compatibility with different fpga solutions low-power cmos eprom process available in 5v version only programming support by leading programmer manufacturers. design support using the xilinx alliance and foundation series software packages. description the xc1700d qpro? family of configuration proms pro- vide an easy-to-use, cost-effective method for storing xilinx fpga configuration bitstreams. when the fpga is in master serial mode, it generates a configuration clock that drives the prom. a short access time after the rising clock edge, data appears on the prom data output pin that is connected to the fpga d in pin. the fpga generates the appropriate number of clock pulses to complete the configuration. once configured, it disables the prom. when the fpga is in slave serial mode, the prom and the fpga must both be clocked by an incoming signal. multiple devices can be concatenated by using the ceo output to drive the ce input of the following device. the clock inputs and the data outputs of all proms in this chain are interconnected. all devices are compatible and can be cascaded with other members of the family. for device programming, either the xilinx alliance? or the foundation? series development systems compiles the fpga design file into a standard hex format which is then transferred to most commercial prom programmers. qpro family of xc1700d qml configuration proms ds070 (v2.1) june 1, 2000 product specification r figure 1: simplified block diagram (does not show programming circuit) eprom cell matrix address counter ce data oe output clk v cc v pp gnd ds027_01_021500 tc oe reset/ oe/ reset or ceo
qpro family of xc1700d qml configuration proms 2 www.xilinx.com ds070 (v2.1) june 1, 2000 1-800-255-7778 product specification r pin description data data output, 3-stated when either ce or oe are inactive. during programming, the data pin is i/o. note that oe can be programmed to be either active high or active low. clk each rising edge on the clk input increments the internal address counter, if both ce and oe are active. reset/oe when high, this input holds the address counter reset and 3-states the data output. the polarity of this input pin is programmable as either reset/oe or oe/reset . to avoid confusion, this document describes the pin as reset/oe , although the opposite polarity is possible on all devices. when reset is active, the address counter is held at zero, and the data output is put in a high-impedance state. the polarity of this input is programmable. the default is active high reset, but the preferred option is active low reset , because it can be driven by the fpgas init pin. the polarity of this pin is controlled in the programmer inter- face. this input pin is easily inverted using the xilinx hw-130 programmer software. third-party programmers have different methods to invert this pin. ce when high, this pin disables the internal address counter, 3-states the data output, and forces the device into low-i cc standby mode. ceo chip enable output, to be connected to the ce input of the next prom in the daisy chain. this output is low when the ce and oe inputs are both active and the internal address counter has been incremented beyond its terminal count (tc) value. in other words: when the prom has been read, ceo will follow ce as long as oe is active. when oe goes inactive, ceo stays high until the prom is reset. note that oe can be programmed to be either active high or active low. v pp programming voltage. no overshoot above the specified max voltage is permitted on this pin. for normal read oper- ation, this pin must be connected to v cc . failure to do so may lead to unpredictable, temperature-dependent opera- tion and severe problems in circuit debugging. do not leave v pp floating! v cc and gnd v cc is positive supply pin and gnd is ground pin. prom pinouts capacity number of configuration bits, including header for xilinx fpgas and compatible proms pin name 8-pin data 1 clk 2 reset/oe (oe/reset )3 ce 4 gnd 5 ceo 6 v pp 7 v cc 8 device configuration bits xc1736d 36,288 xc1765d 65,536 XC17128D 131,072 xc17256d 262,144 device configuration bits prom xc3000/a series 14,819 to 94,984 xc1765d to XC17128D xc4000 series 95,008 to 247,968 XC17128D to xc17256d xq4005e 95,008 XC17128D xq4010e 178,144 xc17256d xq4013e 247,968 xc17256d
qpro family of xc1700d qml configuration proms ds070 (v2.1) june 1, 2000 www.xilinx.com 3 product specification 1-800-255-7778 r controlling proms connecting the fpga device with the prom. the data output(s) of the prom(s) drives the d in input of the lead fpga device. the master fpga cclk output drives the clk input(s) of the prom(s). the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). the reset /oe input of all proms is best driven by the init output of the lead fpga device. this connection assures that the prom address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a v cc glitch. other methods ? such as driving reset /oe from ldc or system reset ? assume the prom internal power-on-reset is always in step with the fpga ? s internal power-on-reset. this may not be a safe assumption. the prom ce input can be driven from either the ldc or done pins. using ldc avoids potential contention on the d in pin. the ce input of the lead (or only) prom is driven by the done output of the lead fpga device, provided that done is not permanently grounded. otherwise, ldc can be used to drive ce , but must then be unconditionally high during user operation. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary supply current of 10 ma maximum. fpga master serial mode summary the i/o and logic functions of the configurable logic block (clb) and their associated interconnections are established by a configuration program. the program is loaded either automatically upon power up, or on command, depending on the state of the three fpga mode pins. in master serial mode, the fpga automatically loads the configuration pro- gram from an external memory. the xilinx proms have been designed for compatibility with the master serial mode. upon power-up or reconfiguration, an fpga enters the master serial mode whenever all three of the fpga mode-select pins are low (m0=0, m1=0, m2=0). data is read from the prom sequentially on a single data line. syn- chronization is provided by the rising edge of the temporary signal cclk, which is generated during configuration. master serial mode provides a simple configuration inter- face. only a serial data line and two control lines are required to configure an fpga. data from the prom is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of cclk. if the user-programmable, dual-function d in pin on the fpga is used only for configuration, it must still be held at a defined level during normal operation. xilinx fpgas take care of this automatically with an on-chip default pull-up resistor. programming the fpga with counters unchanged upon completion when multiple fpga-configurations for a single fpga are stored in a prom, the oe pin should be tied low. upon power-up, the internal address counters are reset and con- figuration begins with the first program stored in memory. since the oe pin is held low, the address counters are left unchanged after configuration is complete. therefore, to reprogram the fpga with another program, the done line is pulled low and configuration begins at the last value of the address counters. this method fails if a user applies r eset during the fpga configuration process. the fpga aborts the configuration and then restarts a new configuration, as intended, but the prom does not reset its address counter, since it never saw a high level on its oe input. the new configuration, therefore, reads the remaining data in the prom and inter- prets it as preamble, length count etc. since the fpga is the master, it issues the necessary number of cclk pulses, up to 16 million (2 24 ) and done goes high. however, the fpga configuration will be completely wrong, with potential contentions inside the fpga and on its output pins. this method must, therefore, never be used when there is any chance of external reset during configuration. cascading configuration proms for multiple fpgas configured as a daisy-chain, or for future fpgas requiring larger configuration memories, cas- caded proms provide additional memory. after the last bit from the first prom is read, the next clock signal to the prom asserts its ceo output low and disables its data line. the second prom recognizes the low level on its ce input and enables its data output. see figure 2 . after configuration is complete, the address counters of all cascaded proms are reset if the fpga r eset pin goes low, assuming the prom reset polarity option has been inverted. to reprogram the fpga with another program, the done line goes low and configuration begins where the address counters had stopped. in this case, avoid contention between data and the configured i/o use of d in .
qpro family of xc1700d qml configuration proms 4 www.xilinx.com ds070 (v2.1) june 1, 2000 1-800-255-7778 product specification r figure 2: master serial mode. the one-time-programmable prom supports automatic loading of configuration programs. multiple devices can be cascaded to support additional fpgas. an early done inhibits the prom data output one cclk cycle before the fpga i/os become active. din dout cclk init done prom data clk ce ce fpga (low resets the address pointer) * for mode pin connections, refer to the appropriate fpga data sheet. vcc v cc v cc optional daisy-chained fpgas with different configurations optional slave fpgas with identical configurations reset reset ds027_02_052200 cclk (output) din dout (output) oe/reset modes* v pp v pp cascaded serial memory data clk ceo oe/reset 3.3v 4.7k
qpro family of xc1700d qml configuration proms ds070 (v2.1) june 1, 2000 www.xilinx.com 5 product specification 1-800-255-7778 r standby mode the prom enters a low-power standby mode whenever ce is asserted high. the output remains in a high impedance state regardless of the state of the oe input. programming the devices can be programmed on programmers supplied by xilinx or qualified third-party vendors. the user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. the wrong choice can permanently damage the device. important:
qpro family of xc1700d qml configuration proms 6 www.xilinx.com ds070 (v2.1) june 1, 2000 1-800-255-7778 product specification r xc1736d, xc1765d, XC17128D and xc17256d absolute maximum ratings operating conditions note: must be connected to v cc dc characteristics over operating condition symbol description units v cc supply voltage relative to gnd ? 0.5 to +7.0 v v pp supply voltage relative to gnd ? 0.5 to +12.5 v v in input voltage relative to gnd ? 0.5 to v cc + 0.5 v v ts voltage applied to high-z output ? 0.5 to v cc + 0.5 v t stg storage temperature (ambient) ? 65 to +150
qpro family of xc1700d qml configuration proms ds070 (v2.1) june 1, 2000 www.xilinx.com 7 product specification 1-800-255-7778 r ac characteristics over operating condition (1,2) symbol description xc1736d xc1765d XC17128D xc17256d units min max min max t oe oe to data delay - 45 - 25 ns t ce ce to data delay - 60 - 45 ns t cac clk to data delay - 150 - 50 ns t oh data hold from ce , oe , or clk (3) 0-0-ns t df ce or oe to data float delay (3,4) -50-50ns t cyc clock periods 200 - 80 - ns t lc clk low time (3) 100 - 20 - ns t hc clk high time (3) 100 - 20 - ns t sce ce setup time to clk (to guarantee proper counting) 25 - 20 - ns t hce ce hold time to clk (to guarantee proper counting) 0 - 0 - ns t hoe oe hold time (guarantees counters are reset) 100 - 20 - ns notes: 1. ac test load = 50 pf 2. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 3. guaranteed by design, not tested. 4. float delays are measured with 5 pf ac loads. transition is measured at 200mv from steady state active levels. reset/oe ce clk data t ce t oe t lc t sce t sce t hce t hoe t cac t oh t df t oh t hc ds027_03_021500 t cyc
qpro family of xc1700d qml configuration proms 8 www.xilinx.com ds070 (v2.1) june 1, 2000 1-800-255-7778 product specification r ac characteristics over operating condition when cascading (1,2) symbol description xc1736d xc1765d XC17128D xc17256d units min max min max t cdf clk to data float delay (3,4) - 50 - 50 ns t ock clk to ceo delay (3) - 65 - 30 ns t oce ce to ceo delay (3) - 45 - 35 ns t ooe reset/oe to ceo delay (3) - 40 - 30 ns notes: 1. ac test load = 50 pf 2. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. 3. guaranteed by design, not tested. 4. float delays are measured with 5 pf ac loads. transition is measured at 200mv from steady state active levels. reset/oe clk data ce t ooe ceo first bit last bit t oce t ock t cdf ds027_04_021500 t oce
qpro family of xc1700d qml configuration proms ds070 (v2.1) june 1, 2000 www.xilinx.com 9 product specification 1-800-255-7778 r ordering information valid ordering combinations marking information due to the small size of the prom package, the complete ordering part number cannot be marked on the package. the xc prefix is deleted and the package code is simplified. device marking is as follows. revision history the following table shows the revision history for this document XC17128Ddd8m xc17256ddd8m xc1736ddd8m xc1765ddd8m 5962-9561701mpa 5962-9471701mpa xc17256d dd8 m operating range/processing m = military (t c = ? 55
qpro family of xc1700d qml configuration proms 10 www.xilinx.com ds070 (v2.1) june 1, 2000 1-800-255-7778 product specification r
|
